Differential current sensing scheme for magnetic random access memory

ABSTRACT

A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation application of U.S. application Ser.No. 14/987,503 filed on Jan. 4, 2016, which is U.S. application Ser. No.14/611,572 filed on Feb. 2, 2015, which is a continuation application ofU.S. application Ser. No. 13/948,432 filed on Jul. 23, 2013, thedisclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure is generally related to magnetic random accessmemory (MRAM) devices and, in particular, to a current sensing schemefor the MRAM devices.

BACKGROUND

In magnetic random access memories (MRAMs), memory cells are arranged inarrays having rows and columns. In some approaches, with reference to anaccessed memory cell selected from a row and a column, a sense amplifieris used to compare a current flowing through the accessed memory cellagainst a reference current. Ideally, the value of the reference currentis averaged between the currents when the accessed memory cell hascorresponding high and low logic values. To that end, two referencecells are used, one having a low logic value, and one having a highlogic value.

Effectively, the sense amplifier receives one accessed memory cell atone input and two reference cells at another input, and is therefore notsymmetrical. As a result, the sense amplifier experiences unbalancedparasitic decoupling during a transition period after the senseamplifier is turned on, which, in turns, requires a long wait time forthe currents at the two inputs of the sense amplifier to be stabilized.Further, the capacitive loads at the two inputs of the sense amplifierare not equal, and cause inaccuracies in fast dynamic sensing wheninstantaneous current difference is detected and amplified.

At high temperature such as 85° C., non-selected cells in two columnscontaining the reference cells have twice higher leakage current thannon-selected cells in a regular column containing an accessed memorycell. As a result, a higher leakage current in the reference columnsfavors sensing a high logic value and contributes an error when sensinga low logic value.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more embodiments of the disclosure are set forthin the accompanying drawings and the description below. Other featuresand advantages of the disclosure will be apparent from the description,drawings and claims.

FIG. 1 is a schematic circuit diagram of a circuit for performing adifferential current sensing scheme for an MRAM array in accordance withsome embodiments.

FIG. 2 is a schematic circuit diagram of a regular cell for storing abit of data in accordance with some embodiments.

FIG. 3 is a schematic circuit diagram of a dummy cell in accordance withsome embodiments.

FIG. 4 is a schematic circuit diagram illustrating differential currentsensing of the circuit in FIG. 1 under the user mode in accordance withsome embodiments.

FIG. 5 is a schematic circuit diagram illustrating differential currentsensing of the circuit in FIG. 1 under the reference cell mode inaccordance with some embodiments.

FIG. 6 is a schematic circuit diagram of the read multiplexer andassociated circuits in accordance with some embodiments.

FIG. 7 is a schematic circuit diagram of the current sense amplifierwith mode selection in accordance with some embodiments.

FIG. 8 is a timing diagram of some signals during differential currentsensing in accordance with some embodiments.

Like reference symbols in the various drawings indicate like elements.

DETAIL DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawingsare now described using specific languages. It will nevertheless beunderstood that no limitation of the scope of the disclosure is therebyintended. Any alterations and modifications in the describedembodiments, and any further applications of principles described inthis document are contemplated as would normally occur to one ofordinary skill in the art to which the disclosure relates. Referencenumbers may be repeated throughout the embodiments, but this does notnecessarily require that feature(s) of one embodiment apply to anotherembodiment, even if they share the same reference number. It will beunderstood that when an element is referred to as being “connected to”or “coupled to” another element, it may be directly connected to orcoupled to the other element, or intervening elements may be present.

In the below description, a signal is asserted with a logical high valueto activate a corresponding device when the device is active high. Incontrast, the signal is deasserted with a low logical value todeactivate the corresponding device. When the device is active low,however, the signal is asserted with a low logical value to activate thedevice, and is deasserted with a high logical value to deactivate thedevice.

Circuit for Differential Current Sensing Scheme for MRAM

FIG. 1 is a schematic circuit diagram of a circuit 1 for a differentialcurrent sensing scheme for an MRAM array in accordance with someembodiments. FIG. 1 shows an overall structure for the differentialcurrent sensing scheme. In FIG. 1, the circuit 1 includes an MRAM arrayincluding array segments SEG₁ and SEG₂, read multiplexers 14 and 24 forthe array segments SEG₁ and SEG₂, respectively, current sense amplifiers(CSAs) with mode selection 12 and 22 for the array segments SEG₁ andSEG₂, respectively, and an intermediate switch MS between the two arraysegments SEG₁ and SEG₂.

The array segment SEG₁ includes N regular columns Col₁[0] to Col₁[N−1],a reference column RCol₀, and a plurality of dummy columns DCol. Theregular columns Col₁[0] to Col₁[N−1] include a plurality of rows ofregular cell segments, and each regular cell segment includes aplurality of regular cells 162 for storing data. FIG. 2 is a schematiccircuit diagram illustrating a regular cell 162 for storing a bit ofdata in accordance with some embodiments. The regular cell 162 includesan MTJ element 1622 and a pass gate 1624. In a standard configuration asshown, a free layer 16222 of the MTJ element 1622 is coupled to a bitline BL of a regular column containing the regular cell 162, a fixedlayer 16224 of the MTJ element 1622 is coupled to one of a source and adrain of the pass gate 1624. The other of the source and drain of thepass gate 1624 is coupled to a sense line SL of the regular columncontaining the regular cell 162. A double arrow in the free layer 16222is used. to represent that a magnetization vector of the free layer16222 can be parallel or anti-parallel to that of a fixed layer 16224,which is represented by a single arrow, depending on a logic value ofthe bit stored. Alternatively, in a reverse configuration, the freelayer 16222 is coupled to one of a source and. a drain of the pass gate1624 and the fixed layer 16224 is coupled to the bit line BL of theregular cell 162. The rest of the configuration stays the same. The passgate 1624 is controlled by a word line WI, coupled with a gate of thepass gate 1624 for selecting a row of the array segment SEG₁. Forsimplicity, in FIG. 1, a bit line BL and a source line SL, describedwith reference to FIG. 2, of a regular column Col₁[0], . . . , orCol₁[N−1] are represented by a line connecting the regular cells in thecorresponding column and the read multiplexer 14. Further, a regularcell 162 of the regular column Col₁[0], or Col[N−1] is represented by anMTJ element 1622. The MTJ element 1622 indicates whether a cell is aregular cell, a reference cell or a dummy cell. The reference columnRCol₀ includes reference cells 166 similar to the regular cell 162 inFIG. 2. Each of the reference cells 166 stores the logic low value, asindicated by parallel magnetization vectors in the reference cell 166.

Symmetric to the array segment SEG₁, the array segment SEG₂ includes Nregular columns Col₂[0] to Col₂[N−1], a reference column RCol₁, and aplurality of dummy columns DCol. The array segment SEG₂ is differentfrom the array segment SEG₁ in that the reference column RCol₁ includesreference cells 266 each of which stores the logic high value, asrepresented by anti-parallel magnetization vectors in the reference cell266. In some embodiments, reference columns have some cells with onelogic value and the rest of the cells with an opposite logic value. Insuch embodiments, a reference cell in a selected row from the segmentSEG₁ and a reference cell in a selected row from the segment SEG₂ haveopposite logic values.

Both the array segment SEG₁ and the array segment SEG₂ include dummycolumns DCol. FIG. 3 is a schematic circuit diagram illustrating a dummycell 164 in a dummy column DCol in FIG. 1 in accordance with someembodiments. The dummy cell 164 includes an MTJ element 1642 and a passgate 1644. Similar to the regular cell 162 in FIG. 2, the MTJ element1642 and the pass gate 1644 are connected in series. Further, two endsof the series-connected MTJ element 1642 and pass gate 1644 are coupledto a bit line GBL and a source line GSL of the dummy column DCol,respectively. The bit line GBL and the source line GSL are grounded.Therefore, no read or write operation is performed on the dummy cell164, and the magnetization vectors of the MTJ element 1642 becomeirrelevant and are shaded. For simplicity, in FIG. 1, a bit line GBL anda source line GSL, described with reference to FIG. 3, of a dummy columnDCol are represented by a line connecting the dummy cells in thecorresponding dummy column without connecting to the read multiplexer14, and a dummy cell 164 of the dummy column DCol is represented by ashaded MU element 1642.

In FIG. 1, the array segment SEG₁ is arranged to begin with a dummycolumn DCol, followed by the regular columns Col₁[0] to Col₁[N−1],another dummy column DCol, and then the reference column RCol₀. Thearray segment SEG₁ is followed by the array segment SEG₂ which isarranged to begin with a dummy column DCol, followed by the referencecolumn RCol₁, another dummy column DCol, and then the regular columnsCol₂[0] to Col₂[N−1]. The array segment SEG₂ is again be followed byanother array segment (not shown) similar to the array segment SEG₁.Therefore, each of the regular column Col₁[0] to Col₁[N−1], referencecolumn RCol₀, reference column RCol₁ and the regular column Col₂[0] toCol₂[N−1] is sandwiched between two of the dummy columns DCol, and arethereby shielded.

In each segment SEG₁ or SEG₂ during sensing, only one selected regularcolumn Col₁[i] or Col₂[_(j)] and the reference column RCol₀ or RCol₁ areactive. Other non-selected regular columns Col₁[0] to Col₁[i−1] andCol₁[i+1] to Col₁[N−1] and other non-selected regular columns Col₂[0] toCol₂[j−1] and Col₂[j+1] to Col₂[N−1] stay at some potential, e.g., atground in some embodiments. In order to keep dynamic capacitances foractive columns that are not surrounded, and thus not shielded, byunselected columns, dummy columns DCol are used to shield the activecolumns, which include, a selected regular column Col₁[i] in the regularcolumns Col₁[0] to Col₁[N−1], the reference column RCol₀, and a selectedregular column Col₂[j] in the regular columns Col₂[0] to Col₂[N−1]. Insome embodiments, if the selected regular column Col₁[i] or Col₂[j] issurrounded by unselected regular columns Col₁[m−1] and Col₁[i+1], orCol₂[j−1] and Col₂[j+1], the selected regular column Cola or Col₂[j] isshielded. If, however, the selected regular column Col₁[i] or Col₂[j] isnot surrounded by unselected regular columns, a dummy column DCol isused in conjunction with the unselected regular column to surround theactive column and thus shield the active column. In some embodiments asillustratively shown in FIG. 1, dummy columns DCol. are inserted atwhere the active column is not surrounded by unselected columns duringsensing, including, for example, column Col₁[0], Col₁[N−1], RCol₀,Col₂[0] or Col₂[N−1]. For another example, a dummy column DCol isinserted between the reference columns RCol₀ and RCol₁, because bothreference columns RCol₀ and. RCol₁ are active at the same time. A dummycolumn DCol is inserted between the regular column Col₁[N−1] and thereference column RCol₀, because both the regular columns Col₁[N−1] andthe reference column RCol₀ can be active at the same time. Further, adummy column DCol is inserted between the regular column Col₂[0] and thereference column RCol₁ because both the regular column Col₂[0] and thereference column RCol₁ can be active at the same time

The read multiplexer 14 receives the regular columns Col₁[0] toCol₁[N−1], the reference column RCol₀, the read enable signal RDEN, anda column address Y₁[N:0] as inputs. In response to the read enablesignal RDEN, the read multiplexer 14 selectively couples one of theregular columns Col₁[0] to Col[N−1] to a data output RD₁, and couplesthe reference column RCol₀ to a reference output REF₀ based on thecolumn address Y₁[N:0]. Similarly, the read multiplexer 24 receives theregular columns Col₂[0] to Col₂[N−1], the reference column RCol₁, theread enable signal RDEN, and a column address Y₂[N:0] as inputs. inresponse to the read enable signal RDEN, the read multiplexer 24selectively couples one of the regular columns Col₂[0] to Col₂[N−1] to adata output RD₂, and couples the reference column RCol₁ to a referenceoutput REF₁ based on the column address Y₂[N:0].

The CSA with mode selection 12 has three inputs coupled to the dataoutput RD₁ of the read multiplexer 14, the reference output REF₀ of theread multiplexer 14, and the reference output REF₁ of the readmultiplexer 24, and generates an output RDO₁. Symmetrically, the CSAwith mode selection 22 has three inputs coupled to the data output RD₂of the read multiplexer 24, the reference output REF₁ of the readmultiplexer 24, and the reference output REF₀ of the read multiplexer14, and generates an output RDO₂. The CSAs 12 and 22 operate in twomodes, a user mode and a reference cell mode. The user mode is forreading data bits stored in a regular cell in the array segment SEG₁ anda regular cell in the second array segment SEG₂, respectively. Thereference cell mode is for checking reference bits stored in a referencecell in the reference column RCol₀ and a reference cell in the referencecolumn RCol₁, respectively. The CSA 12 receives two control signals, asense amplifier select signal SASEL₁ and a reference mode signal REFMDfor the user mode and the reference cell mode. Similarly, the CSA 22receives two control signals, a sense amplifier select signal SASEL₂ andthe reference mode signal REFMD for the user mode and the reference cellmode. In the user mode, the signal REFMD is deasserted, and both signalsSASEL₁ and SASEL₂ are asserted to select both the CSAs 12 and 22. In thereference cell mode, the signal REFMD is asserted, and. one of thesignals SASEL₁ and SASEL₂ is asserted to select one of the CSAs 12 and22. Detailed operations of the user mode and the reference cell mode arediscussed with reference to FIGS. 4 and 5, respectively.

The intermediate switch MS couples the reference output REF₀ of the readmultiplexer 14 to the reference output REF₁ of the read multiplexer 24if the reference mode signal REFMD is deasserted, and disconnects thereference output REF₀ of the read multiplexer 14 from the referenceoutput REF₁ of the read multiplexer 24 if the reference mode signalREFMD is asserted. In some embodiments, the intermediate switch MS isnot used.

FIG. 4 is a schematic circuit diagram illustrating differential currentsensing of the circuit 1 in FIG. 1 under the user mode, in accordancewith some embodiments. In the user mode, the read multiplexer 14 in FIG.1 couples a regular cell 162 of a selected regular column Col₁[i] to thedata output RD₁ of the read multiplexer 14, and couples a reference cell166 of the reference column RCol₀ to the reference output REF₀ of theread multiplexer 14. For simplicity, in FIG. 4, the data output RD₁ andthe reference output REF₀ are shown, but the read multiplexer 14 is notshown. Similarly, the read multiplexer 24 couples a regular cell 262 ofa selected regular column Col₂[j] to the data output RD₂ of the readmultiplexer 24, and couples a reference cell 266 to the reference columnRCol₁ to the reference output REF₁ of the second read multiplexer 24.For simplicity, in FIG. 4, the data output RD₂ and the reference outputREF₁ are shown, but the read multiplexer 24 is not shown. In accordancewith some embodiments, the selected regular cell 162 or 262 and thereference cell 166 or 266 are in the same row to compensate resistanceof metal routing in columns. For illustration purposes, the cells in thefirst row are selected in each column. However, any row could beselected and/or different rows in different array segments could beselected. The data output RD₁ and the reference output REF₀ of the readmultiplexer 14 and the reference output REF₁ of the read multiplexer 24are coupled to the three inputs of the CSA 12, respectively. The dataoutput RD₂ and the reference output REF₁ of the read multiplexer 24 andthe reference output REF₀ of the read multiplexer 14 are coupled. to thethree inputs of the CSA 22, respectively.

The CSA 12 includes a CSA 122 and a mode multiplexer 124. The modemultiplexer 124 includes four switches S₁₂₁, S₁₂₂, S₁₂₃ and S₁₂₄. In theuser mode, the switch S₁₂₁ connects the regular cell 162 in the selectedregular column Col₁[i] to a node SD₁ of the CSA 12, the switch S₁₂₂disconnects the reference cell 166 in the reference column RCol₀ fromthe node SD₁, the switch S₁₂₃ connects the reference cell 166 in thereference column RCol₀ to a node SDB₁ of the CSA 12, and the switch S₁₂₄connects the reference column RCol₁ to the node SDB₁. A first currentflows through the node SD₁, the switch S₁₂₁, a switch S_(142,) or S₁₄₄of the read multiplexer 14 in FIG. 6, the sense line SL in FIG. 2, thepass gate 1624, the MTJ element 1622 and the bit line BL of the regularcell 162, some other circuitry related to writing, and finally to groundVSS. A second current flows through the node SDB₁, the switch S₁₂₃, theswitch S₁₄₆ in FIG. 6, a sense line, a pass gate, an MTJ element, and abit line of the reference cell 166 in FIG. 1, some other circuitryrelated to writing and finally to ground VSS. The reference cell 166,the sense line, the pass gate, the MJT element, and the bit line of thereference cell 166 are similar to the cell 162, the sense line SL, thepass gate 1624, the MJT element 1622, and the bit line BL in FIG. 2,respectively. The CSA 122 compares the first current at the node SD₁against the second current at the second node SDB₁ to generate theoutput RDO₁.

Symmetrically, the CSA 22 includes a CSA 222 and a mode multiplexer 224.The mode multiplexer 224 includes four switches S₂₂₁, S₂₂₂, S₂₂₃ andS₂₂₄. In the user mode, the switch S₂₂₁ connects the selected regularcolumn Col₂[j] to a node SD₂ of the CSA 22, the switch S₂₂₂ disconnectsthe reference column RCol₁ from the node SD₂, the switch S₂₂₃ connectsthe reference column RCol₁ to a node SDB₂ of the CSA 22, and the switchS₂₂₄ connects the reference column RCol₀ to the node SDB₂. Current flowsfrom the node SD₂ and the node SDB, of the CSA 22 to ground VSS aresimilar to those of the CSA 12 discussed above, except components in thearray segment SEG₁ in FIG. 1 are replaced by corresponding components inthe array segment SEG₂. The CSA 222 compares the current at the node SD₂against the current at the node SDB₂ to generate the output RDO₂.

In the user mode, the switch MS couples the reference column RCol₀ tothe reference column RCol₁, thereby forming a common node between thereference columns RCol₀ and RCol₁. In some embodiments illustrated inFIG. 4, the switch MS is used because in the CSA 12, the switch S₁₂₃ andthe switch S₁₂₄ couple both the reference columns RCol₀ and RCol₁ to thenode SDB₁. Further, in the CSA 22, the switch S₂₂₃ and the switch S₂₂₄couple both the reference columns RCol₀ and RCol₁ to the node SDB₂. Theswitch MS further ensures that a current at the common node is asummative current of a current flowing in the reference column RCol₀corresponding to the logic low value and a current flowing in the secondreference column RCol₁ corresponding to the logic high value.

In the user mode, two CSAs 122 and 222 are used to achieve differentialcurrent sensing for reading two data bits. Each of the CSAs 122 and 222effectively has similar amount of currents flowing through the node SD₁or SD₂ and the node SDB₁ or SDB₂. Because a current I₀ flowing throughthe reference cell 166 in the reference column RCol₀ and a current I₁flowing through the reference cell 266 in the reference column RCol₁ aresummed and are equally divided between the CSAs 122 and 222, the currentflowing through the node SDB₁ or SDB₂ of the CSA 122 or 222 is0.5(I₀+I₁). Therefore, a magnitude of the current flowing through thenode SDB₁ or SDB₂ is similar to that of the current flowing through thenode SD₁ or SD₂, which is equal to either I₀ or I₁ depending on the databit stored in the regular cell 162 or 262. In contrast to asymmetricalmagnitudes of currents that flow through two inputs of the current senseamplifier in other approaches, the currents flowing through the node SD₁or SD₂ and the node SDB₁ or SDB₂ of the present disclosure issymmetrical in magnitude.

In the user mode, each of the CSAs 122 and 222 effectively hassymmetrical capacitive loading to the node SD₁ or SD₂ and the node SDB₁or SDB₂. Because the nodes SDB₁ and SDB₂ of both of the CSAs 122 and 222are coupled. to the two reference columns RCol₀ and RCol₁, an effectivecapacitive loading to the node SDB₁ or SDB₂ of the CSA 122 or 222 isthat of one column. Compared to a capacitive loading to the node SD₁ orSD₂ of the CSA 122 or 222, which is that of one regular column Col₁[i]or Col₂[j], the effective capacitive loading to the second node SDB₁ orSDB₂ is also that of one column, and is therefore symmetrical.

In the user mode, each of the CSAs 122 and 222 effectively hassymmetrical leakage currents with respect to the node SD₁ or SD₂, andthe node SDB₁ or SDB₂. Because the nodes SDB₁ and SDB₂ of both the CSAs122 and 222 are coupled to the two reference columns RCol₀ and RCol₁,the leakage currents from the unselected cells in the two referencecolumns RCol₀ and RCol₁ are summed and are equally divided between thetwo nodes SDB₁ and SDB₂. Therefore, each of the node SDB₁ or SDB₂ iseffectively experiencing the leakage current of one column. Compared toa leakage current flowing through the node SD₁ or SD₂, which is theleakage current of one regular column Col₁[i] or Col₂[j], the effectiveleakage current through the second node SDB₁ or SDB₂ is also one columnand is therefore symmetrical. Because of comparable current magnitudesand symmetrical capacitive loading for the node SD₁ or SD₂ and the nodeSDB₁ or SDB₂, accuracy and noise immunity of differential currentsensing are improved and dynamic sensing becomes possible withembodiments of the present disclosure.

FIG. 5 is a schematic circuit diagram illustrating differential currentsensing of the circuit 1 in FIG. 1 wider the reference cell mode inaccordance with some embodiments. In the reference cell mode, the readmultiplexer 14 in FIG. 1 couples a reference cell 166 of the referencecolumn RCol₀ to the reference output REF₀ of the read multiplexer 14.Further, the read multiplexer 24 couples a reference cell 266 of thereference column RCol₁ to the reference output REF₁ of the readmultiplexer 24. For illustration purposes, the cells in the first roware selected in each column. However, any row could be selected and/ordifferent rows in different array segments could be selected. Thereference output REF₀ of the read multiplexer 14 and the referenceoutput REF₁ of the read multiplexer 24 are coupled to two of the threeinputs of the CSA 12. As an example, the CSA 12 is selected. Either theCSA 12 or the CSA 22 can be selected in the reference cell mode.

In the multiplexer 124, the switch S₁₂₁ disconnects the data output RD₁of the read multiplexer 14 in FIG. 1 from the node SD₁, the switchS₁₂₂connects the reference cell 166 in the reference column RCol₀ to thenode SD₁, the switch S₁₂₃ disconnects the reference cell 166 in thereference column RCol₀ from the node SDB₁ and the switch S₁₂₄ connectsthe reference cell 266 in the reference column RCol₁ to the node SDB₁.Current flows from the node SD₁ and the node SDB₁ of the CSA 12 toground VSS are similar to those in the user mode, except the regularcell 162 is replaced by the reference cell 166 in the reference columnRCol₀ and the reference cell 166 in the reference column RCol₀ isreplaced by the reference cell 266 in the reference column RCol₁. TheCSA 122 compares the current at the node SD₁ against the current at thenode SDB₁ to generate the output RDO₁.

In the reference cell mode, the switch MS disconnects the referencecolumn RCol₀ from the reference column RCol₁, thereby breaking thecommon node between the reference columns RCol₀ and RCol₁.

Further, one CSA 122 is used to achieve differential current sensing forchecking reference bits in the reference cells of two reference columnsRCol₀ and RCol₁. A current I₀ flowing through the reference cell 166 inthe reference column RCol₀ and the node SD₁ of the CSA 122 is similar inmagnitude to the current I₁ flowing through the reference cell 266 inthe reference column RCol₀ and the node SDB₁ of the CSA 122. Also, acapacitive loading to the node SD₁ is that of one reference column RCol₀and a capacitive loading to the node SDB₁ is that of one referencecolumn RCol₁. Therefore, the capacitive loading to the two nodes SD₁ andSDB₁ are symmetrical. Furthermore, a leakage current flowing through thenode SD₁ flows from one reference column RCol₀ and a leakage currentflowing through the node SDB₁ flows from one reference column RCol₁.Hence, the leakage currents flowing through the two nodes SD₁ and SDB₁are symmetrical. Because of comparable current magnitudes and symmetriccapacitive loading for the node SD₁ and the node SDB₁, accuracy andnoise immunity of differential current sensing are improved.

FIG. 6 is a schematic circuit diagram illustrating the read multiplexer14 in FIG. 1 and associated circuits, in accordance with someembodiments. For illustration purposes, the read multiplexer 14 isshown. The same structure applies to the read multiplexer 24. The readmultiplexer 14 includes a plurality of switches S₁₄₂ to S₁₄₄corresponding to the regular columns Col₁[0] to Col₁[N−1], respectively.The switches S₁₄₂ to S₁₄₄ are configured to selectively couple one ofthe regular columns Col₁[0] to Col₁[N−1] to the data output RD₁ of theread multiplexer 14 in response to a corresponding control signals CS₀to CS_(N-1). The read multiplexer 14 further includes an additionalswitch S₁₄₆ corresponding to the reference column RCol₀ in FIG. 1. Theswitch S₁₄₆ is configured to selectively couple the reference columnRCol₀ to the reference output REF₀ of the read multiplexer 14 inresponse to a control signal CS_(N). In some embodiments, the switchS₁₄₆ is not used, and the reference column RCol₀ is directly coupled tothe reference output REF₀. However, the switch S₁₄₆ is used in FIG. 6 tohelp in maintaining symmetry with respect to the outputs RD₁ and REF₀.In response to the read enable signal RDEN, the control signals CS₀ toCS_(N) are provided by control logic blocks 142 to 144 based on thecolumn address Y₁[N:0].

Because the switches S₁₄₂ to S₁₄₄ for the regular columns Col₁[0] toCol₁[N−1] are coupled to the data output RD₁ and the switch S₁₄₆ for thereference column RCol₀ is coupled to the reference output REF₀,capacitive loading to the data output RD₁ and the reference output REF₀are imbalanced. Since the data output RD₁ and the reference output REF₀are coupled to the node SD₁ and the node SDB₁ f the CSA 122 in FIG. 4 inthe user mode, maintaining balance between the two outputs RD₁ and REF₀helps in improving sensing accuracy and immunity to noise. In order tobalance the loading of the switches S₁₄₂ ^(to S) ₁₄₄ to the data outputRD₁, a plurality of dummy switches DS₁₄₂ to DS₁₄₄ coupling to thereference output REF₀ and corresponding to the switches S₁₄₂ to S₁₄₄ areintroduced.

Similarly, in order to balance the loading of the switch S₁₄₆ to thereference output REF₀, a dummy switch DS₁₄₆ coupling to the data outputRD₁ and corresponding to the switch S₁₄₆ is introduced. The dummyswitches DS₁₄₂ to DS₁₄₆ are maintained in a turned off state. In someembodiments where an NMOS transistor is used as a dummy switch S₁₄₆, thegate of the NMOS transistor is grounded.

In accordance with some embodiments, the switches S₁₄₂ to S₁₄₆ arecoupled to the sense lines SL₀ to SL_(N-1) of the regular columnsCol₁[0] to Col₁[N−1] and the sense line SL of the reference columnRCol_(o), respectively. Further, the dummy switches DS₁₄₂ to DS₁₄₆ arecoupled to the bit lines BL₀ to BL_(N-1) of the regular columns Col₁[0]to Col₁[N−1] and the bit line BL_(N) of the reference column RCol₀,respectively. In some embodiments, the dummy switches DS₁₄₂ to DS₁₄₀ arenot coupled to the bit lines BL₀ to BL_(N-1). However coupling the dummyswitches DS₁₄₂ to DS₁₄₆ to bit lines BL₀ to BL_(N-1) simplifies buildingequivalent load for the data output RD₁ and the reference output REF₀.

FIG. 7 is a schematic circuit diagram illustrating the CSA 12 in FIG. 1,in accordance with some embodiments. For illustration purposes, the CSA12 is shown. The same structure applies to the CSA 22. The CSA 12includes the CSA 122 and the mode multiplexer 124. The CSA 122 is adynamic current sense amplifier that detects instantaneous currentdifference. The CSA 122 includes a pre-charge device 1226, a clampingdevice 1224, a pull-up device 1222, a differential amplifier 1220, alatch 1228 and control logic gates Q₁ and Q₂. The mode multiplexer 124includes 6 NMOSs M16, M17, M18, M19, M20 and M21 and control logic gatesQ₃, Q₄, Q₅ and Q₆.

The mode multiplexer 124 shown in FIG. 7 is an implementation of themode multiplexer 124 in FIG. 4 and FIG. 5 at the transistor level. TheNMOSs M16 and M17 correspond to the switch S₁₂₁, the NMOS M18corresponds to the switch S₁₂₂, the NMOS M19 corresponds to the switchS₁₂₃, and the NMOSs M20 and M21 correspond to the switch S₁₂₄. Drainsand sources of the NMOSs M16 and M17 are coupled to the node SD₁ of theCSA 12 and the data output RD₁ of the read multiplexer 14 in FIG. 1,respectively. A drain and a source of the NMOS M18 are coupled to thenode SD₁ and the reference output REF₀ of the read multiplexer 14,respectively. A drain and a source of the NMOS M19 are coupled to thenode SDB₁ and the reference output REF₀ of the read multiplexer 14,respectively. Drains and sources of the NMOSs M20 and M21 are coupled tothe node SDB₁ and the reference output REF₁ of the read multiplexer 24in FIG. 1, respectively. For symmetry purposes, the NMOSs M16, M17 andM18 are coupled to the node SD₁, and the NMOSs M19, M20 and M21 arecoupled to the node SDB₁.

Gates of the NMOSs M16 and M17 are coupled to an output of the controllogic gate Q₃. A gate of the NMOS M18 is coupled to an output of thecontrol logic gate Q₄. A gate of the NMOS M19 is coupled to an output ofthe control logic gate Q₆. A gate of the NMOS M20 is coupled to thesense amplifier select signal SASEL₁ and a gate of the NMOS M21 isgrounded. The control logic gate Q₄ receives the signal SASEL₁ and thesignal REFMD as inputs. The control logic gates Q₃ and Q₆ receive thesignal SASEL₁ as one input, and a complemented output of the control.logic gate Q₄ through the control logic gate Q, as the other input. Inaccordance with some embodiments, the control logic gates Q₃, Q₄, Q₅ andQ₆ are two AND gates, an inverter and an AND gate, respectively.Therefore, when the signal SASEL₁ is asserted and the signal REFMD isdeasserted in the user mode, the NMOSs M16 and M17 couple the dataoutput RD₁ of the read multiplexer 14 to the node SD₁, the NMOS M19couples the reference output REF₀ of the read multiplexer 14 to the nodeSDB₁, and the NMS M20 couples the reference output REF₁ of the readmultiplexer 24 to the node SDB₁. In contrast, when the signal SASEL₁ isasserted and the signal REFMD is asserted in the reference cell mode,the NMOS M18 couples the reference output REF₀ of the read multiplexer14 to the node SD₁, and the NMOS M20 couples the reference output REF₁of the read multiplexer 24 to the node SDB₁. When the CSA 22 is selectedin the reference cell mode, the signal SASEL₁ is deasserted and all ofthe NMOSs M16 to M21 are turned off.

The pre-charge device 1226 of the CSA 122 is configured to pre-chargeboth the node SD₁ and the node SDB₁ to ground VSS in response to theassertion of a pre-charge signal PCH. The pre-charge device 1226includes two NMOSs M14 and M15 having sources coupled to ground VSS andan NMOS M13 coupling the drains of the two NMOSs M14 and M15 in responseto the assertion of the pre-charge signal PCH.

The pull-up device 1222 of the CSA 122 pulls up both the node SD₁ and.the node SDB₁ through the clamping device 1224 when a sense amplifierenable signal SAEN and the pre-charge signal PCH are deasserted. Thepull-up device 1222 includes two PMOSs M9 and M10 having sources coupledto a power supply VDD, drains coupled to the node SD₁ and the node SDB₁through the clamping device 1224, respectively, gates coupled togetherand to an output of the control logic gate Q₂ receiving the signal SAENand the signal PCH. In accordance with some embodiments, the controllogic gate Q₂ is an OR gate.

The clamping device 1224 of the CSA 122 is configured to clamp voltagesat the node SD₁ and the node SDB₁ to a predetermined level that does notoverwrite a data bit stored in a memory cell when the pull-up device1222 is pulling up. In some embodiments, the predetermined level is0.2V. The clamping device 1224 includes two NMOSs M11 and M12 configuredto couple the drains of the PMOSs M9 and M10 of the pull-up device 1222to the node SD₁ and the node SDB₁, respectively. Gates of the two NMOSsM11 and M12 are coupled together and to a clamping voltage controlsignal VCL which controls impedance of the two NMOSs M11 and M12 toprovide the desired voltage drop with respect to VDD through the NMOSsM11 and M12.

The differential amplifier 1220 of the CSA 122 is configured to convertdifference in currents at the node SD₁ and the node SDB ₁ receivedthrough the clamping device 1224 to difference in voltages, and amplifythe difference in voltages. The differential amplifier 1220 includes apair of PMOSs M1 and M2, a pair of PMOSs M3 and M4, a pair of NMOSs MSand M6, and a pair of NMOSs M7 and M8.

The pair of PMOSs Mi and M2 is configured to provide power supply VDD tothe other elements of the differential amplifier 1220 in response to thedeassertion of the pre-charge signal PCH. In the pair of PMOSs Ml andM2, sources are coupled to the power supply VDD, drains are coupledtogether and to both of sources of the pair of PMOSs M3 and M4, andgates are coupled together and to the pre-charge signal PCH.

The pair of PMOSs M3 and M4 is configured to convert difference incurrents at the node SD₁ and the node SDB₁ received through the clampingdevice 1224 to difference in voltages. In the pair of PMOSs M3 and M4,the sources are coupled to the power supply VDD through the pair ofPMOSs M1 and M2, a drain of the PMOS M4 is coupled to a gate of the PMOSM3 and to the node SD₁, and a drain of the PMOS M3 is coupled to a gateof the PMOS M4 and to the node SDB₁. Therefore, the pair of PMOSs M3 andM4 is cross-coupled. The drains of the pair of PMOSs M3 and M4 serve asdifferential voltage outputs SO and SOB of the differential amplifier1220, respectively.

The pair of NMOSs M5 and M6 is configured to couple drains of the pairof NMOSs M7 and M6 to the drains of the pair of PMOSs M3 and M4 inresponse to the assertion of a latch enable signal LAEN and theassertion of the sense amplifier select signal SASEL₁. Gates of the pairof NMOSs M5 are coupled together and to the control logic gate Q₁receiving the latch enable signal LAEN and the sense amplifier selectsignal SASEL₁. In accordance with some embodiments, the control logicgate Q₁ is an AND gate.

The pair of NMOSs M7 and M8 forms a cross-coupled inverters with thepair of PMOSs M3 and M4 when the latch enable signal LAEN and the senseamplifier select signal SASEL₁ are asserted. The cross-coupled invertersserve to amplify the voltage difference developed.

at the differential voltage outputs SO and SOB.

The latch 1228 of the CSA 122 is configured to latch the differentialvoltage outputs SO and SOB when the latch enable signal LAEN and thesense amplifier select signal SASEL₁ are asserted. In accordance withsome embodiments, the latch 1228 is an SR latch, of which a set input Sreceives the differential voltage output SO, a reset input R receivesthe other differential voltage output SOB, an enable input E receivesthe output of the control logic gate Q, and a data output Q serves asthe output RDO₁ of the CSA 12.

Signals for Differential Current Sensing Scheme for MRAM

FIG. 8 is a timing diagram 800 illustrating some signals in FIG. 1 andin FIG. 7 during differential current sensing, in accordance with someembodiments. For illustration purposes, the signals of the CSA 12 areused, and the same tinting diagram 800 also applies to the CSA 22.Additionally, the timing diagram 800 also applies to both the user modeand the reference cell mode. During a pre-charge phase before a timet₈₁₀, the pre-charge signal PCH is asserted with a high logical value.The node SD₁ and the node SDB₁ are pre-charged to ground VSS by thepre-charge device 1226 in FIG. 7. Therefore, both the node SD₁ and thenode SDB₁ start from ground VSS before currents are applied to them.

When the read enable signal RDEN is asserted with a high logical valueat the time t₈₁₀, the pre-charge signal PCH is deasserted and. acharging current stabilization phase begins. Two columns are selectedbased on the asserted bits Y₁[m] and Y₁[n] of the column address Y₁[N:0]by the read multiplexer 14 in FIG. 1. Further, the two columns are iscoupled to the node SD₁ and the node SDB₁, respectively. The two columnsinclude a regular column and the reference column in the user mode, andinclude both reference columns in the reference cell mode. The pull-updevice 1222 starts charging the node SD₁ and the node SDB₁ through theclamping device 1224 until currents through the node SD₁ and the nodeSDB₁ reach stabilization at a time t₈₂₀. When stabilization is reached,voltages at the two nodes SD₁ and SDB₁ are at a predetermined clampingvoltage of about 0.2V in some embodiments, depending on the clampingvoltage control signal VCL to the clamping device 1224. Between timet₈₁₀ and t₈₂₀, the differential amplifier 1220, with the pull-up device1222, charges the differential voltage outputs SO and SOB. By the timet₈₂₀, the outputs SO and SOB have reached supply voltage VDD.

At the time t₈₂₀, the sense amplifier enable signal SAEN is asserted,and an I to V conversion phase begins. The pull-up device 1222 stopscharging the node SD₁, the node SD₂, and the outputs SO and. SOB. Thedifference in resistance between the two selected columns causes thecurrent to flow through the node SD₁ to be smaller than that through thenode SDB₁. Therefore, the voltage at the node SD₁ drops at a rate slowerthan that of at the node SDB₁, which, in turn, causes the voltage at theoutput SO drops at a rate slower than that of at the output SOB. Becausethe output SOB drops faster, the PMOS M3 is strongly turned, on whilethe PMOS M4 is weakly turned on. The PMOS M4 pulls the output SO towardsVDD while the PMOS M3 slows down the voltage drop at the SOB. Therefore,the difference in voltages at the outputs SO and SOB amplifies. This inturn causes similar transitions at the node SD_(;) and the node SDB₁.

Then, at a time t₈₃₀, the latch enable signal LAEN is asserted and adata latching phase begins. The cross-coupled inverters formed by thePMOSs M3 and M4 and the NMOSs M7 and, M8 are in operation. Because theoutput SO is close to VDD, the PMOS M3 is turned off and the NMOS M7 isturned on and thereby pulling the output SOB to ground. VSS. This inturn causes the PMOS M4 to turn on more strongly. The positive feedbackof the cross-coupled inverters M3 and M4 further amplifies thedifference in voltages at the outputs SO and SOB. Meanwhile, the latch1228 latches the outputs SO and SOB and generates the output RDO₁ of theCSA 12. Then, at a time t₈₄₀, the pre-charge signal PCH is asserted toindicate that the differential current sensing for a read operation iscompleted.

In some embodiments, a circuit comprises a first and a second referencecells and a current sense amplifier. The first and second referencecells are configured to store a first and a second logic values,respectively. The current sense amplifier is configured to couple thefirst reference cell to the first node of the current sense amplifier,and. couple the second reference cell to the second node of the currentsense amplifier for reading bits stored in the first reference cell andthe second reference cell.

In some embodiments, a circuit comprises an array segment, a first and asecond reference columns, and a current sense amplifier. The first andsecond reference columns are configured to store a first and a secondlogic values, respectively. The current sense amplifier is configuredwith a first node and a second node for currents therethrough to becompared with each other. The current sense amplifier is configured tocouple one column of the array segment to the first node of the currentsense amplifier, and to couple the first and second reference columns tothe second node of the current sense amplifier for reading data bitsstored in a cell in the array segment.

In some embodiments, a method includes: coupling a first reference cellto a first node of a current sense amplifier; coupling a secondreference cell to a second node of the current sense amplifier; andreading bits stored in the first reference cell and the second referencecell based on currents through the first and second nodes of the currentsense amplifier.

A number of embodiments of the disclosure have been described. It willnevertheless be understood that various modifications may be madewithout departing from the spirit and scope of the disclosure. Forexample, some transistors are shown to be N-type and some others areshown to be P-type, but the disclosure is not limited to such aconfiguration. Embodiments of the disclosure are applicable invariations and/or combinations of transistor types. A bit line BL or GBLis also called a data line because each of the bit line BL or GBLcarries data for a corresponding cell.

The above description includes exemplary operations, but theseoperations are not necessarily required to be performed in the ordershown. Operations may be added, replaced, changed order, and/oreliminated as appropriate, in accordance with the spirit and scope ofthe disclosure. Accordingly, the scope of the disclosure should bedetermined with reference to the following claims, along with the fullscope of equivalences to which such claims are entitled.

What is claimed is:
 1. A circuit, comprising: a first and a secondreference cells configured to store a first and a second logic values,respectively; and a current sense amplifier, configured to couple thefirst reference cell to a first node of the current sense amplifier, andcouple the second reference cell to a second node of the current senseamplifier for reading bits stored in the first reference cell and thesecond reference cell.
 2. The circuit according to claim 1, furthercomprising: a cell segment comprising a cell; a plurality of switches,coupled to the first node of the current sense amplifier, and configuredto selectively couple the cell of the cell segment to the first node ofthe current sense amplifier; and a plurality of loads, coupled to thesecond node of the current sense amplifier.
 3. The circuit according toclaim 2, wherein the plurality of switches further comprise anadditional switch; the additional switch is coupled to the second nodeof the current sense amplifier, and is configured to selectively couplethe first reference cell to the second node of the current senseamplifier; the plurality of loads further comprise an additional load;and the additional load is coupled to the first node of the currentsense amplifier.
 4. The circuit according to claim 2, wherein for eachswitch of the plurality of switches, one end of the switch is coupled tothe first node of the current sense amplifier, and the other end of theswitch is coupled to a source line of the cell of the cell segmentcorresponding to the switch; and for each load, of the plurality ofloads, one end of the load is coupled, to the second node of the currentsense amplifier, and the other end of the load is unconnected or iscoupled to a data line of the cell of the cell segment corresponding tothe load.
 5. The circuit according to claim 1, further comprising: afirst switch configured to disconnect the cell of the cell segment fromthe first node of the current sense amplifier in a first mode, andcouple the cell of the cell segment to the first node of the currentsense amplifier in a second mode; a second switch configured to couplethe first reference cell to the first node of the current senseamplifier in the first mode and disconnect the first reference cell fromthe first node of the current sense amplifier in the second mode; athird switch configured to disconnect the first reference cell from thesecond node of the current sense amplifier in the first mode and couplethe first reference cell to the second node of the current senseamplifier in the second mode; and a fourth switch configured to couplethe second reference cell to the second node of the current senseamplifier in both the first mode and the second mode.
 6. The circuitaccording to claim 5, wherein the first switch comprises a firsttransistor and a second transistor coupled in parallel and bothconfigured to be turned off in the first mode and turned on in thesecond mode; the second switch comprises a third transistor configuredto be turned on in the first mode and turned off in the second mode; thethird switch comprises a fourth transistor configured to be turned offin the first mode and turned on in the second mode; and the fourthswitch comprises a fifth transistor and a sixth transistor coupled inparallel, wherein the fifth transistor is configured to be turned on inboth the first mode and the second mode; and the sixth transistor isconfigured to be turned off in both the first mode and the second mode.7. The circuit according to claim 5, further comprising: a fifth switchconfigured to form a common node between the first reference cell andthe second reference cell in the first mode, and to disconnect the firstreference cell from the second reference cell in the second mode.
 8. Thecircuit according to claim 2, further comprising: a plurality of dummycells, wherein any of the cell segment, the first reference cell and thesecond reference cell is sandwiched between two of the dummy cells. 9.The circuit according to claim 2, wherein the cell segment and the firstreference cell are in the same row.
 10. A circuit, comprising: an arraysegment; a first and a second reference columns configured to store afirst and a second logic values, respectively; and a current senseamplifier, configured with a first node and a second. node for currentstherethrough to be compared with each other, wherein the current senseamplifier is configured to couple one column of the array segment to thefirst node of the current sense amplifier, and couple the first andsecond reference columns to the second node of the current senseamplifier for reading data bits stored in a cell in the array segment.11. The circuit according to claim 10, further comprising: a pluralityof switches, coupled to the first node of the current sense amplifier,and configured to selectively couple a column of the array segment tothe first node of the current sense amplifier; and a plurality of loadscoupled to the second node of the current sense amplifier.
 12. Thecircuit according to claim 11, wherein the plurality of switches furthercomprise an additional switch; the additional switch is coupled to thesecond node of the current sense amplifier, and is configured toselectively couple the first reference column to the second node of thecurrent sense amplifier; the plurality of loads further comprise anadditional load; and the additional load is coupled to the first node ofthe current sense amplifier.
 13. The circuit according to claim 11,wherein for each switch of the plurality of switches, one end of theswitch is coupled to the first node of the current sense amplifier, andthe other end of the switch is coupled to a source line of the column ofthe array segment corresponding to the switch; and for each load of theplurality of loads, one end of the load is coupled to the second node ofthe current sense amplifier, and the other end of the load isunconnected or is coupled to a data line of the column of the arraysegment corresponding to the load.
 14. The circuit according to claim10, further comprising: a first switch configured to disconnect thecolumn of the array segment from the first node of the current senseamplifier in a first mode, and couple the column of the array segment tothe first node of the current sense amplifier in a second mode; a secondswitch configured to couple the first reference column to the first nodeof the current sense amplifier in the first mode and disconnect thefirst reference cell from the first node of the current sense amplifierin the second mode; a third switch configured to disconnect the firstreference column from the second node of the current sense amplifier inthe first mode and couple the first reference column to the second nodeof the current sense amplifier in the second mode; and a fourth switchconfigured to couple the second reference column to the second node ofthe current sense amplifier in both the first mode and the second mode.15. The circuit according to claim 14, wherein the first switchcomprises a first transistor and a second transistor coupled in paralleland both configured to be turned off in the first mode and turned on inthe second mode; the second switch comprises a third transistorconfigured to be turned on in the first mode and turned, off in thesecond mode; the third switch comprises a fourth transistor configuredto be turned off in the first mode and turned on in the second mode; andthe fourth switch comprises a fifth transistor and a sixth transistorcoupled in parallel, wherein the fifth transistor is configured to beturned on in both the first mode and the second mode; and the sixthtransistor is configured to be turned off in both the first mode and thesecond mode.
 16. The circuit according to claim 14, further comprising:a fifth switch configured to form a common node between the firstreference column and the second reference column in the first mode, andto disconnect the first reference column from the second referencecolumn in the second mode.
 17. The circuit according to claim 10,further comprising: a plurality of dummy columns, wherein any of thearray segment, the first reference column, and the second referencecolumn is sandwiched between two of the dummy columns.
 18. A methodcomprising: coupling a first reference cell to a first node of a currentsense amplifier; coupling a second reference cell to a second node ofthe current sense amplifier; and reading bits stored in the firstreference cell and the second reference cell based on currents throughthe first and second nodes of the current sense amplifier.
 19. Themethod according to claim 18, further comprising: selectively coupling acell of a cell segment to the first node of the current sense amplifier;selectively coupling first and second reference cells to the second nodeof the current sense amplifier; and generating differential voltageoutputs based on currents through the first and second nodes of thecurrent sense amplifier for reading data bits stored in the cell in thearray segment.
 20. The method according to claim 19, wherein thecoupling the first reference cell to the current sense amplifiercomprises: turning on a first switch coupled between the first node andthe first reference cell in response to a first state of a mode signal;and turning off a second switch coupled between the first node and thecell of the cell segment in response to the first state of the modesignal; and the generating the differential voltage outputs based oncurrents through the first and second nodes of the current senseamplifier comprises: charging the first node and the second of thecurrent sense amplifier; and enabling sensing currents through the firstand second nodes of the current sense amplifier to generate thedifferential voltage outputs.